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lt3030 1 3030f for more information www.linear.com/3030 typical a pplica t ion fea t ures descrip t ion dual 750ma/250ma low dropout, low noise, micropower linear regulator the lt ? 3030 is a dual, micropower, low noise, low dropout linear regulator. the device operates with either common or independent input supplies for each channel, over a 1.8v to 20 v input voltage range. output 1/output 2 supply 750ma/250ma respectively with a typical dropout voltage of 300 mv. with an external 10 nf bypass capacitor, output noise is only 20v rms over a 10 hz to 100 khz bandwidth. designed for use in battery-powered systems, the low 120a/75a quiescent current makes it an ideal choice. in shutdown, quiescent current drops to less than 1a. shutdown control is independent for each channel and its precision logic threshold allows for voltage lockout functionality. the lt3030 includes a pwrgd flag for each channel to indicate output regulation. the lt3030 optimizes stability and transient response with low esr ceramic output capacitors, requiring a minimum of only 10f/3.3f. internal circuitry provides reverse - battery protection , reverse-current protection, current limiting with foldback and thermal shutdown with hysteresis. the adjustable output voltage device has a 1.220 v reference voltage. the lt3030 is offered in the thermally enhanced 20-lead tssop and 28- lead, low profile (4mm 5mm 0.75mm) qfn packages. 2.5v in to 1.8v/1.5v application a pplica t ions n output current: 750ma/250ma n low dropout voltage: 300mv n low noise: 20v rms (10hz to 100khz) n low quiescent current: 120a/75a n wide input voltage range: 1.8v to 20v n adjustable output: 1.220v reference voltage n shutdown quiescent current: <1a n stable with 10f/3.3f minimum output capacitor n stable with ceramic, tantalum or aluminum electrolytic capacitors n precision threshold for shutdown logic or uvlo function n pwrgd flag for each output n reverse battery and reverse output-to-input protection n current limit with foldback and thermal shutdown n thermally enhanced 20-lead tssop and 28-lead (4mm 5mm) qfn packages n general purpose linear regulator n battery-powered systems n microprocessor core/logic supplies n post regulator for switching supplies n tracking/sequencing power supplies dropout voltage vs load current l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. output current (ma) 0 dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 450 150 3030 ta01b 750 300 600 375 75 675 225 525 out1 t j = 25c out2 lt3030 gnd 1m in1 in2 shdn1 shdn2 pwrgd1 pwrgd2 out1 byp1 adj1 out2 byp2 adj2 1m 3.3f 10f 3.3f 10nf 3030 ta01a v in 2.5v v out1 1.8v 750ma v out2 1.5v 250ma 113k 1% 237k 1% 10nf 54.9k 1% 237k 1%
lt3030 2 3030f for more information www.linear.com/3030 a bsolu t e maxi m u m r a t ings in 1, in 2 pin voltage ................................................ 22 v out 1, out 2 pin voltage ......................................... 22 v input - to - output differential voltage ........................ 22 v adj 1, adj 2 pin voltage ............................................ 9 v byp 1, byp 2 pin voltage ........................................ 0.6 v shdn 1 , shdn 2 pin voltage .................................... 22 v pwrgd 1, pwrgd 2 pin voltage .................... 22 v , C 0.3 v output short - circuit duration .......................... in definite 9 10 top view gnd 29 ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 out1 out1 gnd gnd gnd gnd out2 out2 pwrgd1 in1 in1 gnd gnd in2 in2 pwrgd2 byp1 adj1 gnd gnd gnd shdn1 byp2 adj2 gnd gnd gnd shdn2 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 33c/w, , jc = 3.4c/w exposed pad (pin 29) is gnd, must be soldered to pcb fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 adj1 byp1 out1 out1 gnd gnd out2 out2 byp2 adj2 shdn1 pwrgd1 in1 in1 gnd gnd in2 in2 pwrgd2 shdn2 gnd 21 t jmax = 150c, ja = 28c/w, , jc = 10c/w exposed pad (pin 21) is gnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range lt3030eufd#pbf lt3030eufd#trpbf 3030 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3030iufd#pbf lt3030iufd#trpbf 3030 28-lead (4mm 5mm) plastic qfn C40c to 125c lt3030efe#pbf lt3030efe#trpbf lt3030fe 20-lead plastic tssop C40c to 125c lt3030ife#pbf lt3030ife#trpbf lt3030fe 20-lead plastic tssop C40c to 125c lt3030hfe#pbf lt3030hfe#trpbf lt3030fe 20-lead plastic tssop C40c to 150c lt3030mpfe#pbf lt3030mpfe#trpbf lt3030fe 20-lead plastic tssop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature ( notes 2, 12) e -/ i- grade .......................................... C 40 c to 125 c h- grade ............................................. C 40 c to 150 c mp - grade .......................................... C 55 c to 150 c storage temperature range qfn / tssop package ............................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ( tssop only ) ........................................................ 30 0 c (note 1)
lt3030 3 3030f for more information www.linear.com/3030 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2). parameter conditions min typ max units minimum input voltage (notes 3, 11) output 1, i load = 750ma output 2, i load = 250ma l l 1.7 1.7 2.2 2.2 v v adj1, adj2 pin voltage (notes 3, 4) v in = 2v, i load = 1ma output 1, 2.2v < v in1 < 20v, 1ma < i load < 750ma output 2, 2.2v < v in2 < 20v, 1ma < i load < 250ma l l 1.208 1.196 1.196 1.220 1.220 1.220 1.232 1.244 1.244 v v v line regulation (note 3) ?v in = 2v to 20v, i load = 1ma l 0.5 5 mv load regulation (note 3) output 1, v in1 = 2.2v, ?i load = 1ma to 750ma v in1 = 2.2v, ?i load = 1ma to 750ma l 2 6 10 mv mv output 2, v in2 = 2.2v, ?i load = 1ma to 250ma v in2 = 2.2v, ?i load = 1ma to 250ma l 2 6 10 mv mv dropout voltage (output 1) v in1 = v out1(nominal) (notes 5, 6, 11) i load = 10ma i load = 10ma l 0.13 0.20 0.28 v v i load = 100ma i load = 100ma l 0.17 0.23 0.33 v v i load = 500ma i load = 500ma l 0.27 0.32 0.43 v v i load = 750ma i load = 750ma l 0.3 0.36 0.48 v v dropout voltage (output 2) v in2 = v out2(nominal) (notes 5, 6, 11) i load = 10ma i load = 10ma l 0.14 0.20 0.28 v v i load = 50ma i load = 50ma l 0.18 0.24 0.32 v v i load = 100ma i load = 100ma l 0.22 0.28 0.38 v v i load = 250ma i load = 250ma l 0.3 0.36 0.48 v v gnd pin current (output 1) v in1 = v out1(nominal) (notes 5, 7) i load = 0ma i load = 10ma i load = 100ma i load = 500ma i load = 750ma l l l l l 120 420 2 9 15 300 800 3.8 17 27 a a ma ma ma gnd pin current (output 2) v in2 = v out2(nominal) (notes 5, 7) i load = 0ma i load = 10ma i load = 50ma i load = 100ma i load = 250ma l l l l l 75 330 1 1.8 5 200 600 1.8 3.4 9 a a ma ma ma output voltage noise c out = 10f, c byp = 10nf, i load = full current (note 13) bw = 10hz to 100khz 20 v rms adj1/adj2 pin bias current (notes 3, 8) 30 100 na shutdown threshold v out = off to on v out = on to off hysteresis (note 2) l l 1.09 0.5 1.21 0.83 0.38 1.33 v v v shdn1/shdn2 pin current (note 10) v shdn1 , v shdn2 = 0v v shdn1 , v shdn2 = 20v l l 0 0.85 0.5 3 a a quiescent current in shutdown (per channel) v in = 20v, v shdn1 = 0v, v shdn2 = 0v 0.3 2 a pwrgd trip point % of nominal output voltage, output rising l 86 90 94 % pwrgd trip point hysteresis (note 2) % of nominal output voltage, output falling 1.6 % p wrgd output low v oltage i pwrgd = 100a l 15 150 mv pwrgd leakage current v shdn = 0v, v pwrgd = 20v l 1 a
lt3030 4 3030f for more information www.linear.com/3030 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3030 is tested and specified under pulse load conditions such that t j t a . the lt3030e is 100% tested at t a = 25c and performance is guaranteed from 0c to 125c. performance of the lt3030e over the full C40c to 125c operating junction temperature range is assured by design, characterization and correlation with statistical process controls. the lt3030i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3030mp is 100% tested and guaranteed over the C55c to 150c operating junction temperature range. the lt3030h is tested at 150c operating junction temperature. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: the lt3030 is tested and specified for these conditions with the adj1/adj2 pin connected to the corresponding out1/out2 pin. note 4: maximum junction temperature limits operating conditions. the regulated output voltage specification does not apply for all possible combinations of input voltage and output current . when operating at maximum input voltage, limit the output current range. when operating at maximum output current, limit the input voltage range. note 5: to satisfy minimum input voltage requirements, the lt3030 is tested and specified for these conditions with an external resistor divider (two 243k resistors) for an output voltage of 2.447v. the external resistor divider adds 5a of dc load on the output. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2). parameter conditions min typ max units ripple rejection v in = 2.72v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load = full current (note 13) 50 60 db v in = v out(nominal) + 1v, v ripple = 50mv rms f ripple = 1mhz, i load = full current (note 13) 50 db current limit (note 9) output 1, v in1 = 6v, v out1 = 0v v in1 = 2.2v, ?v out1 = C0.1v l l 1.1 800 1.4 1.7 a ma output 2, v in2 = 6v, v out2 = 0v v in2 = 2.2v, ?v out2 = C0.1v l l 350 270 420 490 ma ma input reverse leakage current v in = C20v, v out = 0v l 1 ma reverse output current v out = 1.220v, v in = 0v 0.5 10 a note 6: dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage equals: v in C v dropout . note 7: gnd pin current is tested with v in = 2.447v and a current source load. this means the device is tested while operating in its dropout region or at the minimum input voltage specification. this is the worst-case gnd pin current. the gnd pin current decreases slightly at higher input voltages. total gnd pin current equals the sum of output 1 and output 2 gnd pin currents. note 8: adj1/adj2 pin bias current flows into the pin. note 9: the lt3030 contains current limit foldback circuitry. see the typical performance characteristics section for current limit as a function of the v in C v out differential voltage. note 10: shdn1 and shdn2 pin current flows into the pin. note 11: the lt3030 minimum input voltage specification limits dropout voltage under some output voltage/load conditions. see the curve of minimum input voltage in the typical performance characteristics section. note 12: the lt3030 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature exceeds the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 13: the full current for i load is 750ma and 250ma for output 1 and output 2 respectively.
lt3030 5 3030f for more information www.linear.com/3030 typical p er f or m ance c harac t eris t ics out1 dropout voltage vs temperature out2 guaranteed dropout voltage out2 dropout voltage vs temperature quiescent current adj1/adj2 pin voltage quiescent current out1 typical dropout voltage out1 guaranteed dropout voltage t j = 25c, unless otherwise noted. out2 typical dropout voltage output current (ma) 0 dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 450 150 3030 g01 750 300 600 375 75 675 225 525 t j = ?55c t j = 150c t j = 25c t j = 125c output current (ma) 0 guaranteed dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 450 150 3030 g02 750 300 600 375 75 675 225 525 t j = 25c t j = 150c = test points temperature (c) ?75 dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 75 ?25 3030 g03 175 25 125 50 ?50 150 0 100 i l = 750ma i l = 500ma i l = 300ma i l = 100ma i l = 10ma i l = 1ma output current (ma) 0 dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 150 50 3030 g04 250 100 200 125 25 225 75 175 t j = 150c t j = 25c t j = ?55c t j = 125c output current (ma) 0 guaranteed dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 150 50 3030 g05 250 100 200 125 25 225 75 175 t j = 150c t j = 25c = test points temperature (c) ?75 dropout voltage (mv) 500 450 400 350 300 250 200 150 100 50 0 75 ?25 3030 g06 175 25 125 50 ?50 150 0 100 i l = 250ma i l = 175ma i l = 100ma i l = 50ma i l = 10ma i l = 1ma temperature (c) ?75 quiescent current (a) 300 250 200 150 100 50 0 75 ?25 3030 g07 175 25 125 50 ?50 150 0 100 output 1 v shdn1 = v in1 output 2 v shdn2 = v in2 v in1 = v in2 = 6v r l1 = r l2 = 243k; i l1 = i l2 = 5a temperature (c) ?75 adj pin voltage (v) 1.244 1.238 1.232 1.226 1.220 1.214 1.208 1.202 1.196 75 ?25 3030 g08 175 25 125 50 ?50 150 0 100 adj2 adj1 i l1 = i l2 = 1ma input voltage (v) 0 quiescent current (a) 300 250 200 150 100 50 0 12 4 3030 g09 20 8 16 10 2 18 6 14 output 1, v shdn1 = v in1 output 2, v shdn2 = v in2 t j = 25c r l1 = r l2 = 243k; i l1 = i l2 = 5a v out1 = v out2 = 1.220v output 1; v shdn1 = 0v output 2; v shdn2 = 0v
lt3030 6 3030f for more information www.linear.com/3030 typical p er f or m ance c harac t eris t ics out1 gnd pin current out2 gnd pin current out2 gnd pin current out2 gnd pin current shdn1 or shdn2 pin threshold shdn1 or shdn2 pin input current quiescent current in shutdown (per output) out1 gnd pin current out1 gnd pin current t j = 25c, unless otherwise noted. input voltage (v) 0 quiescent current (a) 1.0 0.5 0.4 0.3 0.2 0.9 0.8 0.7 0.6 0.1 0 12 4 3030 g10 20 8 16 10 2 18 6 14 t j = 25c r l1 = r l2 = 243k; i l1 = i l2 = 5a v out1 = v out2 = 1.220v v shdn1 = v shdn2 = 0v input voltage (v) 0 gnd pin current (ma) 2.4 1.5 1.2 0.9 0.6 2.1 1.8 0.3 0 6 2 3030 g11 9 4 8 5 1 3 7 i l1 = 10ma i l1 = 1ma i l1 = 100ma t j = 25c for v out1 = 1.220v input voltage (v) 0 gnd pin current (ma) 27 24 15 12 9 6 21 18 3 0 6 2 3030 g12 9 4 8 5 1 3 7 i l1 = 500ma i l1 = 750ma i l1 = 250ma t j = 25c for v out1 = 1.220v output current (ma) 0 gnd pin current (ma) 27 24 15 12 9 6 21 18 3 0 450 150 3030 g13 750 300 600 675 375 75 225 525 t j = 25c v in1 = v out1(nominal) + 1v input voltage (v) 0 gnd pin current (ma) 1.2 1.0 0.8 0.6 0.4 0.2 0 6 2 3030 g14 9 4 8 5 1 3 7 i l1 = 10ma i l1 = 25ma i l1 = 1ma t j = 25c for v out2 = 1.220v input voltage (v) 0 gnd pin current (ma) 9 8 7 6 4 2 5 3 1 0 6 2 3030 g15 9 4 8 5 1 3 7 i l2 = 100ma i l2 = 50ma i l2 = 250ma t j = 25c for v out2 = 1.220v output current (ma) 0 gnd pin current (ma) 9 8 7 6 4 2 5 3 1 0 150 50 3030 g16 250 100 200 225 125 25 75 175 t j = 25c v in2 = v out2(nominal) + 1v temperature (c) ?75 shdn pin threshold (v) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 75 ?25 3030 g17 175 25 125 50 ?50 150 0 100 on to off off to on v in = 2.2v shdn pin voltage (v) 0 shdn pin input current (a) 2.0 1.0 0.8 0.6 0.4 1.8 1.6 1.4 1.2 0.2 0 12 4 3030 g18 20 8 16 10 2 18 6 14 v in = 2.2v v in = 20v t j = 25c
lt3030 7 3030f for more information www.linear.com/3030 typical p er f or m ance c harac t eris t ics pwrgd1 or pwrgd2 output low voltage out1 current limit out1 current limit out2 current limit out2 current limit reverse current shdn1 or shdn2 pin input current adj1 or adj2 pin bias current pwrgd1 or pwrgd2 trip point t j = 25c, unless otherwise noted. temperature (c) ?75 shdn pin input current (a) 2.0 1.0 0.8 0.6 0.4 1.8 1.6 1.4 1.2 0.2 0 75 ?25 3030 g19 175 25 125 50 ?50 150 0 100 v in = 2.2v, v shdn = 20v v in = 20v v shdn = 2.2v temperature (c) ?75 adj pin bias current (na) 150 75 60 45 30 135 120 105 90 15 0 75 ?25 3030 g20 175 25 125 50 ?50 150 0 100 temperature (c) ?75 pwrgd trip point (% of output voltage) 94 91 90 89 88 93 92 87 86 75 ?25 3030 g21 175 25 125 50 ?50 150 0 100 output rising output falling temperature (c) ?75 pwrgd output low voltage (mv) 150 75 60 45 30 135 120 105 90 15 0 75 ?25 3030 g22 175 25 125 50 ?50 150 0 100 i pwrgd = 100a input voltage (v) 0 current limit (a) 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 12 4 3030 g23 20 8 16 10 2 18 6 14 t j = ?55c t j = 150c t j = 125c v out = 0v t j = 25c temperature (c) ?75 current limit (a) 2.0 1.4 1.2 1.8 1.6 1.0 0.8 0.6 0.4 0.2 0 75 ?25 3030 g24 175 25 125 50 ?50 150 0 100 v in = 6v v in = 18v v out = 0v input voltage (v) 0 current limit (a) 0.60 0.54 0.48 0.42 0.36 0.30 0.24 0.18 0.12 0.06 0 12 4 3030 g25 20 8 16 10 2 18 6 14 t j = ?55c t j = 150c t j = 125c t j = 25c v out = 0v temperature (c) ?75 current limit (a) 0.60 0.54 0.48 0.42 0.36 0.30 0.24 0.18 0.12 0.06 0 75 ?25 3030 g26 175 25 125 50 ?50 150 0 100 v in = 6v v in = 18v v out = 0v output voltage (v) 0 reverse current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 1 3030 g27 9 3 7 4 8 2 6 i adj = flows into adj pin to gnd pin i out = flows into out pin to in pin i adj1 or i adj2 i out1 or i out2 t j = 25c v in1 = v in2 = 0v v adj1 = v out1 v adj2 = v out2
lt3030 8 3030f for more information www.linear.com/3030 typical p er f or m ance c harac t eris t ics out1 input ripple rejection out2 input ripple rejection out2 input ripple rejection out2 input ripple rejection channel-to-channel isolation reverse current out1 input ripple rejection out1 input ripple rejection t j = 25c, unless otherwise noted. temperature (c) ?75 reverse current (a) 500 450 400 350 300 250 200 150 100 50 0 75 ?25 3030 g28 175 25 125 50 150 0 100 i adj = flows into adj pin to gnd pin i out = flows into out pin to in pin i out2 i adj1 or i adj2 i out1 v in1 = v in2 = 0v v adj1 = v out1 = 1.220v v adj2 = v out2 = 1.220v frequency (hz) 10 ripple rejection (db) 100 90 80 70 60 50 40 30 20 10 0 1m 100 3030 g29 10m 10k 100k 1k c out1 = 10f c out1 = 47f c out1 = 22f t j = 25c i l1 = 750ma, c byp1 = 0 v in1 = v out1(nominal) + 1v + 50mv rms ripple frequency (hz) 10 ripple rejection (db) 100 90 80 70 60 50 40 30 20 10 0 1m 100 3030 g30 10m 10k 100k 1k c byp1 = 10nf c byp1 = 100pf c byp1 = 1000pf t j = 25c i l1 = 750ma, c out1 = 22f v in1 = v out1(nominal) + 1v + 50mv rms ripple temperature (c) ?75 ripple rejection (db) 100 90 80 70 60 50 40 30 20 10 0 50 ?50 3030 g31 175 0 25 ?25 150 100 125 75 v in1 = v out1(nominal) + 1.5v + 500mv p-p ripple f = 120hz i l1 = 750ma frequency (hz) 10 ripple rejection (db) 100 90 80 70 60 50 40 30 20 10 0 1m 100 3030 g32 10m 10k 100k 1k c out2 = 3.3f c out2 = 22f c out2 = 10f t j = 25c i l2 = 250ma, c byp2 = 0 v in2 = v out2(nominal) + 1v + 50mv rms ripple frequency (hz) 10 ripple rejection (db) 100 90 80 70 60 50 40 30 20 10 0 1m 100 3030 g33 10m 10k 100k 1k c byp2 = 10nf c byp2 = 100pf c byp2 = 1000pf t j = 25c i l2 = 250ma, c out2 = 10f v in2 = v out2(nominal) + 1v + 50mv rms ripple channel-to-channel isolation temperature (c) ?75 ripple rejection (db) 100 90 80 70 60 50 40 30 20 10 0 50 ?50 3030 g34 175 0 25 ?25 150 100 125 75 v in2 = v out2(nominal) + 1.5v + 500mv p-p ripple f = 120hz i l2 = 250ma frequency (hz) 10 channel-to-channel isolation (db) 100 90 80 70 60 50 40 30 20 10 0 1m 100 3030 g35 10m 10k 100k 1k channel 2 channel 1 given channel is tested with 50mv rms signal on opposing channel, both channels delivering full current t j = 25c 50s/div v out1 100mv/div v out2 100mv/div 3030 g36 c out1 = 10f c out2 = 3.3f c byp1 = c byp2 = 0.01f ?i l1 = 50ma to 750ma ?i l2 = 50ma to 250ma v in = 6v, v out1 = v out2 = 5v
lt3030 9 3030f for more information www.linear.com/3030 typical p er f or m ance c harac t eris t ics output noise spectral density output noise spectral density rms output noise vs bypass capacitor out1 rms output noise vs output current (10hz to 100khz) out2 rms output noise vs output current (10hz to 100khz) out1 or out2 load regulation out1 or out2 line regulation t j = 25c, unless otherwise noted. start-up time from shutdown c byp = 0pf start-up time from shutdown c byp = 0.01f temperature (c) ?75 load regulation (mv) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 50 ?50 3030 g37 175 0 25 ?25 150 100 125 75 ?i l = 1ma to full load temperature (c) ?75 line regulation (mv) 5 4 2 3 1 0 ?2 ?4 ?1 ?3 ?5 50 ?50 3030 g38 175 0 25 ?25 150 100 125 75 ?v in = 2v to 20v frequency (khz) 0.01 output noise spectral density (v/ hz) 10 1 0.1 0.01 0.1 3030 g39 100 10 1 v out = 5v v out = v adj t j = 25c c out = 10f c byp = 0 i l = full load frequency (hz) 0.01 output noise spectral density (v/ hz) 10 1 0.1 0.01 0.1 3030 g40 100 10 1 v out = 5v c byp = 0.01f v out = v adj c byp = 1000pf c byp = 100pf t j = 25c c out = 10f i l = full load c byp (pf) 10 output noise (v rms ) 160 140 120 100 20 40 60 80 0 3030 g41 10000 1000 100 output2 output1 output2 output1 v out = 5v v out = 1.220v t j = 25c c out = 10f i l = full load f bw = 10hz to 100khz output current (ma) 0.01 output noise (v rms ) 160 140 120 100 20 40 60 80 0 3030 g42 1000 100 1010.1 v out1 = 5v v out1 = v adj1 c byp1 = 10nf v out1 = v adj1 c byp1 = 0 v out1 = 5v c byp1 = 0 t j = 25c c out = 10f 1ms/div shdn voltage 2v/div 3030 g44 v in = 2.5v c in = 10f c out = 10f i l = full load t j = 25c v out = 1.5v v out 1v/div 1ms/div shdn voltage 2v/div 3030 g45 v in = 2.5v c in = 10f c out = 10f i l = full load t j = 25c v out = 1.5v v out 1v/div output current (ma) 0.01 output noise (v rms ) 160 140 120 100 20 40 60 80 0 3030 g43 1000 100 1010.1 v out2 = 5v v out2 = v adj2 c byp2 = 10nf v out2 = v adj2 c byp2 = 0 v out2 = 5v c byp2 = 0 t j = 25c c out = 10f
lt3030 10 3030f for more information www.linear.com/3030 typical p er f or m ance c harac t eris t ics out1 transient response c byp = 0pf out1 transient response c byp = 0.01f out2 transient response c byp = 0pf out2 transient response c byp = 0.01f 10hz to 100khz output noise, c byp = 100pf 10hz to 100khz output noise, c byp = 1000pf 10hz to 100khz output noise, c byp = 0.01f t j = 25c, unless otherwise noted. 10hz to 100khz output noise, c byp = 0pf out1 or out2 minimum input voltage temperature (c) ?75 minimum input voltage (v) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 50 ?50 3030 g46 175 0 25 ?25 150 100 125 75 i l = full load i l = 1ma v out1 = v out2 = 1.220v 1ms/div v out 100v/div 3030 g47 c out = 10f i l = full load v out = 5v 1ms/div v out 100v/div 3030 g48 c out = 10f i l = full load v out = 5v 1ms/div v out 100v/div 3030 g49 c out = 10f i l = full load v out = 5v 1ms/div v out 100v/div 3030 g50 c out = 10f i l = full load v out = 5v 200s/div 200mv/div 500ma/div 3030 g51 v in = 6v c in = 22f c out = 22f i l = 100ma to 750ma t j = 25c v out = 5v v out deviation load current deviation 20s/div 50mv/div 500ma/div 3030 g52 v in = 6v c in = 22f c out = 22f i l = 100ma to 750ma t j = 25c v out = 5v v out deviation load current deviation 200s/div 200mv/div 100ma/div 3030 g53 v in = 6v c in = 10f c out = 10f i l = 100ma to 250ma t j = 25c v out = 5v v out deviation load current deviation 20s/div 50mv/div 100ma/div 3030 g54 v in = 6v c in = 10f c out = 10f i l = 100ma to 250ma t j = 25c v out = 5v v out deviation load current deviation
lt3030 11 3030f for more information www.linear.com/3030 p in func t ions out1, out 2 (pins 1, 2, 7, 8/pins 3, 4, 7, 8): output. the out1/out2 pins supply power to the loads. a minimum 10f /3.3 f output capacitor prevents oscillations on out1/out2. applications with large output load transients require larger values of output capacitance to limit peak voltage transients. see the applications information sec- tion for more on output capacitance and on reverse output characteristics. gnd (pins 3, 4, 5, 6, 11, 12, 13, 18, 19, 24, 25, 26, exposed pad pin 29/pins 5, 6, 15, 16, exposed pad pin 21): ground. the exposed pad ( backside) of the qfn and tssop packages is an electrical connection to gnd. to ensure proper electrical and thermal performance, sol- der the exposed pad to the pcb ground and tie directly to gnd pins. connect the bottom of the output voltage setting resistor divider directly to gnd for optimum load regulation performance. in1, in 2 ( pins 20, 21, 16, 17/pins 17, 18, 13, 14): in- put. the in1/in2 pins supply power to each channel. the lt3030 requires a bypass capacitor at the in1/in2 pins if located more than six inches away from the main input filter capacitor. include a bypass capacitor in battery- powered circuits, as a batterys output impedance rises with frequency. a bypass capacitor in the range of 1 f to 10f suffices. the lt3030s design withstands reverse voltages on the in pins with respect to ground and the out pins. in the case of a reversed input, which occurs if a battery is plugged in backwards, the lt3030 acts as if a diode is in series with its input. no reverse current flows into the lt3030 and no reverse voltage appears at the load. the device protects itself and the load. pwrgd1, pwrgd 2 (pins 22, 15/pins 19, 12): power good. the pwrgd flag is an open-collector flag to indicate that the output voltage has increased above 90% of the nominal output voltage. there is no internal pull-up on this pin; a pull-up resistor must be used. the pwrgd pin changes state from an open-collector pull-down to high impedance after the output increases above 90% of the nominal voltage. the maximum pull-down current of the pwrgd pin in the low state is 100a. shdn1, shdn2 (pins 23, 14/pins 20, 11): shutdown. pulling the shdn1 or shdn2 pin low puts its correspond- ing lt3030 channel into a low power state and turns its output off. the shdn1 and shdn2 pins are completely independent of each other, and each shdn pin only affects operation on its corresponding channel. drive the shdn1 and shdn2 pins with either logic or an open collector/ drain with pull-up resistors. the resistors supply the pull-up current to the open collectors/drains and the shdn1 or shdn2 current, typically less than 1 a. if unused, con- nect shdn1 and shdn2 to their corresponding in pins. each channel will be in its low power shutdown state if its corresponding shdn pin is not connected. adj1, adj2 (pins 27, 10/pins 1, 10): adjust pin. these are the error amplifier inputs. these pins are internally clamped to 9 v. a typical input bias current of 30 na flows into the pins ( see curve of adj1/adj2 pin bias current vs temperature in the typical performance characteristics section). the adj1 and adj2 pin voltages are 1.220v referenced to ground and the output voltage range is 1.220v to 19.5v. byp1, byp 2 (pins 28, 9/pins 2, 9): bypass. connecting a capacitor between out and byp of a respective chan- nel bypasses the lt3030 reference to achieve low noise performance, improve transient response and soft-start the output. internal circuitry clamps the byp1/byp2 pins to 0.6v ( one v be ) from ground. a small capacitor from the corresponding output to this pin bypasses the refer- ence to lower the output voltage noise. using a maximum value of 10 nf reduces the output voltage noise to a typical 20v rms over a 10 hz to 100 khz bandwidth. if not used, this pin must be left unconnected. (qfn/tssop)
lt3030 12 3030f for more information www.linear.com/3030 a pplica t ions i n f or m a t ion the lt3030 is a dual 750ma/250ma low dropout regulator with independent inputs, micropower quiescent current and shutdown. the device supplies up to 750ma/250ma from the outputs of channel 1/channel 2 at a typical dropout voltage of 300 mv. the two regulators share common gnd pins and are thermally coupled. however, the two inputs and outputs of the lt3030 operate independently. each channel can be shut down independently, but a thermal shutdown fault on either channel shuts off the output on both channels. the addition of a 10nf reference bypass ca- pacitor lowers output voltage noise to 20 v rms over a 10 hz to 100khz bandwidth. additionally, the reference bypass capacitor improves transient response of the regulator, lowering the settling time for transient load conditions. the low operating quiescent current (120 a/75a for channel 1/2) drops to typically less than 1 a in shutdown. in ad- dition to the low quiescent current, the lt3030 regulator incorporates several protection features that make it ideal for use in battery powered systems. most importantly, the device protects itself against reverse input voltages. adjustable operation each of the lt3030s channels has an output voltage range of 1.220 v to 19.5 v. figure 1 illustrates that the output voltage is set by the ratio of two external resistors. the device regulates the output to maintain the corresponding adj pin voltage at 1.220 v referenced to ground. r1s cur- rent equals 1.220 v/r1. r2s current equals r1s current plus the adj pin bias current. the adj pin bias current, 30na at 25 c, flows through r2 into the adj pin. use the formula in figure 1 to calculate output voltage. linear technology recommends that the value of r1 be less than 243k to minimize errors in the output voltage due to the adj pin bias current. in shutdown, the output turns off and the divider current is zero. curves of adj pin voltage vs temperature and adj pin bias current vs temperature appear in the typical performance characteristics section. linear technology tests and specifies each lt3030 channel with its adj pin tied to the corresponding out pin for a 1.220v output voltage. specifications for output voltages greater than 1.220 v are proportional to the ratio of desired output voltage to 1.220v: v out /1.220v for example, load regulation on out2 for an output cur- rent change of 1 ma to full load current is typically C2mv at v out2 = 1.220v. at v out2 = 2.5v, load regulation is: (2.5 v/1.220v) ? (C2mv) = C4.1mv table 1 shows 1% resistor divider values for some com- mon output voltages with a resistor divider current of approximately 5a. table 1. output voltage resistor divider values v out (v) r1 (k) r2 (k) 1.5 237 54.9 1.8 237 113 2.5 243 255 3 232 340 3.3 210 357 5 200 619 bypass capacitance and low noise performance using a bypass capacitor connected between a channel s byp pin and its corresponding out pin significantly low- ers lt3030 output voltage noise, but is not required in all applications. linear technology recommends a good quality low leakage capacitor. this capacitor bypasses the regulator s reference, providing a low frequency noise pole. a 10nf bypass capacitor introduces a noise pole that decreases output voltage noise to as low as 20v rms . using a bypass capacitor provides the added benefit of improv- ing transient response. with no bypass capacitor and a 10 f output capacitor, a 100 ma to full load step settles to within 1% of its final value in approximately 400s . with the addition of a 10nf bypass capacitor and evaluating the same load step, output voltage excursion stays within 2% ( see transient response in the typical performance characteristics section). using a bypass capacitor makes regulator start- up time proportional to the value of the bypass capacitor. for example, a 10nf bypass capacitor and 10 f output capacitor slow start- up time to 15ms. in1/in2 3030 f01 c out lt3030 out1/out2 v in v out adj1/adj2 gnd r1 r2 v out = 1.220v 1 + r2 r1 ? ? ? ? ? ? + i adj ( ) r2 ( ) v adj = 1.220v i adj = 30na at 25 c output range = 1.220v to 19.5v figure 1. adjustable operation
lt3030 13 3030f for more information www.linear.com/3030 a pplica t ions i n f or m a t ion input capacitance and stability each lt3030 channel is stable with an input capacitor typically between 1 f and 10 f. applications operating with smaller v in to v out differential voltages and that ex- perience large load transients may require a higher input capacitor value to prevent input voltage droop and letting the regulator enter dropout. very low esr ceramic capacitors may be used. however, in cases where long wires connect the power supply to the lt3030s input and ground, use of low value input capaci- tors combined with an output load current of greater than 20ma may result in instability. the resonant lc tank circuit formed by the wire inductance and the input capacitor is the cause and not a result of lt3030 instability. the self-inductance, or isolated inductance, of a wire is directly proportional to its length. however, the wire diameter has less influence on its self inductance. for example, the self-inductance of a 2- awg isolated wire with a diameter of 0.26" is about half the inductance of a 30- awg wire with a diameter of 0.01". one foot of 30- awg wire has 465nh of self-inductance. several methods exist to reduce a wire s self- inductance. one method divides the current flowing towards the lt3030 between two parallel conductors. in this case, placing the wires further apart reduces the inductance; up to a 50% reduction when placed only a few inches apart. splitting the wires connects two equal inductors in parallel. how - ever, when placed in close proximity to each other, mutual inductance adds to the overall self inductance of the wires. the most effective technique to reducing overall inductance is to place the forward and return current conductors ( the input wire and the ground wire) in close proximity. tw o 30- awg wires separated by 0.02" reduce the overall self inductance to about one- fifth of a single wire. if a battery, mounted in close proximity, powers the lt3030 , a 1 f input capacitor suffices for stability. however, if a distantly located supply powers the lt3030, use a larger value input capacitor. use a rough guideline of 1f (in addition to the 1 f minimum) per 8 inches of wire length. the minimum input capacitance needed to stabilize the application also varies with power supply output imped- ance variations. placing additional capacitance on the lt3030s output also helps. however, this requires an order of magnitude more capacitance in comparison with additional lt3030 input bypassing. series resistance be- tween the supply and the lt3030 input also helps stabilize the application; as little as 0.1 to 0.5 suffices. this impedance dampens the lc tank circuit at the expense of dropout voltage. a better alternative is to use higher esr tantalum or electrolytic capacitors at the lt3030 input in place of ceramic capacitors. output capacitance and transient response the lt3030 is stable with a wide range of output capacitors. the esr of the output capacitor affects stability, most nota- bly with small capacitors. linear technology recommends a minimum output capacitor of 10f/3.3f (channel 1 /channel 2) with an esr of 3, or less, to prevent oscil- lations. the lt3030 is a micropower device, and output transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. ceramic capacitors require extra consideration. manufac- turers make ceramic capacitors with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics specify the eia temperature characteristic codes of z5u, y5v, x5r and x7r. z5u and y5v dielectrics provide high c-v products in a small package at low cost, but exhibit strong voltage and temperature coefficients, as shown in figure 2 and figure 3. when used with a 5 v regulator, a 16v 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2f for the applied dc bias voltage and over the operat- ing temperature range. x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. exercise care even when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias ( voltage coefficient) with x5r and x7r capacitors is better than with y5v and z5u capacitors, but can still be significant enough to drop
lt3030 14 3030f for more information www.linear.com/3030 a pplica t ions i n f or m a t ion capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as case size increases. linear technology recommends verifying expected versus actual capacitance values at operating voltage in situ for an application. figure 2. ceramic capacitor dc bias characteristics dc bias voltage (v) change in value (%) 3030 f02 20 0 ?20 ?40 ?60 ?80 ?100 0 4 8 10 2 6 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f figure 3. ceramic capacitor temperature characteristics temperature (c) ?50 40 20 0 ?20 ?40 ?60 ?80 ?100 25 75 3030 f03 ?25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f v out 500v/div 3030 f04 100ms/div c out = 10f c byp = 0.01f i load = 750ma figure 4. noise resulting from tapping on a ceramic capacitor voltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or micro- phone works. for a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. a ceramic capacitor produced the trace's response to light tapping from a pencil, as shown in figure 4. similar vibration induced behavior can masquerade as increased output voltage noise. shutdown/uvlo the shdn pin is used to put the lt3030 into a micropower shutdown state. the lt3030 has an accurate 1.21 v threshold ( during turn- on) on the shdn pin. this threshold can be used in conjunction with a resistor divider from the system input supply to define an accurate undervoltage lockout ( uvlo) threshold for the regulator. the shdn pin current ( at the threshold) needs to be considered when determining the resistor divider network. pwrgd flag the pwrgd flag indicates that the adj pin voltage is within 10% of the regulated voltage. the pwrgd pin is an open-collector output, capable of sinking 100 a of current when the adj pin voltage is below 90% of the regulated voltage. there is no internal pull-up on the pwrgd pin; an external pull-up resistor must be used. as the adj pin voltage rises above 90% of its regulated voltage, the pwrgd pin switches to a high impedance state and the external pull-up resistor pulls the pwrgd pin voltage up. during normal operation, an internal glitch filter prevents the pwrgd pin from switching to a low voltage state if the adj pin voltage falls below the regulated voltage by more than 10% in a short transient (<40 s typical) event. thermal considerations the lt3030s power handling capability limits the maxi- mum rated junction temperature (125 c , lt3030 e/ lt3030 i or 150 c, lt3030h/lt3030mp). tw o components com- prise the power dissipated by each channel:
lt3030 15 3030f for more information www.linear.com/3030 a pplica t ions i n f or m a t ion 1. output current multiplied by the input/output voltage differential: (i out )(v in C v out ), and 2.gnd pin current multiplied by the input voltage : (i gnd )(v in ). ground pin current is found by examining the gnd pin current curves in the typical performance characteristics section. power dissipation for each channel equals the sum of the two components listed above. total power dissipation for the lt3030 equals the sum of the power dissipated by each channel. the lt3030 s internal thermal shutdown circuitry protects both channels of the device if either channel experiences an overload or fault condition. activation of the thermal shutdown circuitry turns both channels off. if the overload or fault condition is removed, both outputs are allowed to turn back on. for continu- ous normal conditions, do not exceed the maximum junction temperature rating of 125c ( lt3030 e/ lt3030 i) or 150c (lt3030h/lt3030mp). carefully consider all sources of thermal resistance from junction-to-ambient, including additional heat sources mounted in proximity to the lt3030. for surface mount devices, use the heat spreading capabilities of the pc board and its copper traces to accomplish heat sinking. copper board stiffeners and plated through-holes can also spread the heat generated by power devices. the following tables list thermal resistance as a function of copper area in a fixed board size. all measurements were taken in still air on a four- layer fr-4 board with 1 oz solid internal planes, and 2 oz external trace planes with a total board thickness of 1.6 mm. for further information on ther - mal resistance and using thermal information, refer to jedec standard jesd51, notably jesd 51-7 and jesd 51-12. table 2. ufd package, 28-lead qfn copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 30c/w 1000mm 2 2500mm 2 2500mm 2 32c/w 225mm 2 2500mm 2 2500mm 2 33c/w 100mm 2 2500mm 2 2500mm 2 35c/w *device is mounted on topside. table 3. fe package, 20-lead tssop copper area board area thermal resistance (junction-to-ambient) topside* backside 2500mm 2 2500mm 2 2500mm 2 25c/w 1000mm 2 2500mm 2 2500mm 2 27c/w 225mm 2 2500mm 2 2500mm 2 28c/w 100mm 2 2500mm 2 2500mm 2 32c/w *device is mounted on topside. the junction-to-case thermal resistance ( jc ), measured at the exposed pad on the back of the die, is 3.4 c/w for the qfn package, and 10c/w for the tssop package. calculating junction temperature example: channel 1s output voltage is set to 1.8 v. channel 2 s output voltage is set to 1.5 v. each channels input voltage is 2.5 v. channel 1 s output current range is 0 ma to 750 ma. channel 2 s output current range is 0ma to 250 ma. the application has a maximum ambient temperature of 50 c. what is the lt3030s maximum junction temperature? the power dissipated by each channel equals: i out(max) (v in C v out ) + i gnd (v in ) where for output 1: i out(max) = 750ma v in = 2.5v i gnd at (i out = 750ma, v in = 2.5v) = 13ma for output 2: i out(max) = 250ma v in = 2.5v i gnd at (i out = 250ma, v in = 2.5v) = 4.5ma so, for output 1: p = 750ma (2.5 v C 1.8v) + 13ma (2.5v) = 0.56w for output 2: p = 250ma (2.5v C 1.5v) + 4.5ma (2.5v) = 0.26w the thermal resistance is in the range of 25 c/w to 35 c/w, depending on the copper area. so, the junction temperature rise above ambient temperature approximately equals: (0.56 w + 0.26w) 30c/w = 24.6c
lt3030 16 3030f for more information www.linear.com/3030 a pplica t ions i n f or m a t ion the maximum junction temperature then equals the maxi- mum ambient temperature plus the maximum junction temperature rise above ambient temperature, or: t jmax = 50c + 24.6c = 74.6c protection features the lt3030 regulator incorporates several protection fea- tures that make it ideal for use in battery - powered circuits . in addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device protects itself against reverse input volt - ages and reverse voltages from output to input. the two regulators have independent inputs, a common gnd pin and are thermally coupled. however, the two channels of the lt3030 operate independently. each channel s output can be shut down independently, and a fault condition on one output does not affect the other output electrically, unless the thermal shutdown circuitry is activated. current limit protection and thermal overload protection protect the device against current overload conditions at each output of the lt3030. for normal operation, do not allow the junction temperature to exceed 125c ( lt3030 e/ lt3030i) or 150c ( lt3030h/lt3030mp). the typical thermal shutdown temperature threshold is 165 c and the circuitry incorporates approximately 5 c of hysteresis. each channels input withstands reverse voltages of 22v. current flow into the device is limited to less than 1 ma ( typically less than 100a ) and no negative voltage appears at the respective channels output. the device protects both itself and the load against batteries that are plugged in backwards. the lt3030 incurs no damage if either channels output is pulled below ground. if the input is left open-circuit, or grounded, the output can be pulled below ground by 22v. the output acts like an open circuit, and no current flows from the output. however, current flows in ( but is limited by) the external resistor divider that sets the output voltage. if the input is powered by a voltage source, the output sources current equal to its current limit capabil- ity and the lt3030 protects itself by its thermal limiting circuitry. in this case, grounding the relevant shdn1 or shdn2 pin turns off its channels output and stops that output from sourcing current. the lt3030 incurs no damage if either adj pin is pulled above or below ground by 9 v. if the input is left open circuit or grounded, the adj pins perform like an open circuit down to C1.5 v, and then like a 1.2 k resistor down to C9 v when pulled below ground. when pulled above ground, the adj pins perform like an open circuit up to 0.5v, then like a 5.7 k resistor up to 3 v, then like a 1.8k resistor up to 9v. in situations where an adj pin connects to a resistor divider that would pull the pin above its 9 v clamp voltage if the output is pulled high, the adj pin input current must be limited to less than 5 ma. for example, assume a resistor divider sets the regulated output voltage to 1.5 v, and the output is forced to 20 v. the top resistor of the resistor divider must be chosen to limit the current into the adj pin to less than 5 ma when the adj pin is at 9 v. the 11v difference between the out and adj pins divided by the 5ma maximum current into the adj pin yields a minimum top resistor value of 2.2k. in circuits where a backup battery is required, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open- circuit. current flow back into the output follows the curve shown in figure 5. if either of the lt3030s in pins is forced below its cor- responding out pin, or the out pin is pulled above its corresponding in pin, input current for that channel typically figure 5. reverse output current output voltage (v) 0 reverse current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 1 3030 f05 9 3 7 4 8 2 6 i adj = flows into adj pin to gnd pin i out = flows into out pin to in pin i adj1 or i adj2 i out1 or i out2 t j = 25c v in1 = v in2 = 0v v adj1 = v out1 v adj2 = v out2
lt3030 17 3030f for more information www.linear.com/3030 a pplica t ions i n f or m a t ion drops to less than 2 a. this occurs if the in pin is con- nected to a discharged ( low voltage) battery, and either a backup battery or a second regulator circuit holds up the output. the state of that channels shdn pin has no effect on the reverse output current if the output is pulled above the input. overload recovery like many ic power regulators, the lt3030 has safe operating area ( soa) protection. the safe area protec- tion decreases current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. the protective design provides some output current at all values of input-to-output voltage up to the specified maximum operational input voltage of 20v. when power is first applied, as input voltage rises, the output follows the input, allowing the regulator to start- up into heavy loads. during start- up, as the input voltage is rising, the input- to- output voltage differential is small, al - lowing the regulator to supply large output currents. with a high input voltage, an event can occur wherein removal of an output short will not allow the output to recover. the event occurs with a heavy output load when the input voltage is high and the output voltage is low. common situations occur immediately after the removal of a short- circuit or if the shutdown pin is pulled high after the input voltage has already been turned on. the load line intersects the output current curve at two points creating two stable output oper - ating points for the regulator. with this double intersection, the input power supply may need to be cycled down to zero and brought up again to make the output recover. typical a pplica t ions coincident tracking supply application 20ms/div v out1 v out2 500mv/div 3030 ta02b 237k 1% 113k 1% 3030 ta02a ltc2923 on 237k 1% 54.9k 1% sdo fb1 gnd ramp gate fb2 v cc track1 rampbuf track2 90.9k 1% 113k 1% 63.4k 1% 54.9k 1% 1m 1m c gate 0.1f 3.3f 0.1f in1 pwrgd1 pwrgd2 shdn1 in2 out1 byp1 adj1 adj2 byp2 out2 shdn2 1m 3.3f 10nf 10nf 3.3f 10f 2.5v 3.3v v out1 1.8v 750ma v out2 1.5v 250ma gnd lt3030 onoff
lt3030 18 3030f for more information www.linear.com/3030 p ackage descrip t ion ufd package 28-lead (4mm 5mm) plastic qfn (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
lt3030 19 3030f for more information www.linear.com/3030 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation cb p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe20 (cb) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation cb
lt3030 20 3030f for more information www.linear.com/3030 ? linear technology corporation 2013 lt 0213 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/3030 r ela t e d p ar t s typical a pplica t ion part number description comments lt1761 100ma, low noise micropower ldo v in : 1.8v to 20v, v out = 1.22v, v do = 0.3v, i q = 20a, i sd <1a, low noise < 20v rms , stable with 1f ceramic capacitors, thinsot? package lt1763 500ma, low noise micropower ldo v in : 1.8v to 20v, v out = 1.22v, v do = 0.3v, i q = 30a, i sd <1a, low noise < 20v rms , s8 package lt1963/ lt1963a 1.5a, low noise, fast transient response ldos v in : 2.1v to 20v, v out(min) = 1.21v, v do = 0.34v, i q = 1ma, i sd < 1a, low noise: < 40v rms , a version stable with ceramic capacitors, dd, to220-5, sot223, s8 packages lt1964 200ma, low noise micropower, negative ldo v in : C2.2v to C20v, v out(min) = 1.21v, v do = 0.34v, i q = 30a, i sd = 3a, low noise: <30v rms , stable with ceramic capacitors, thinsot package lt1965 1.1a, low noise, fast transient response ldo v in : 1.8v to 20v, v out(min) = 1.20v, v do = 0.3v, i q = 0.5ma, i sd < 1a, low noise: < 40v rms , stable with ceramic capacitors, 3mm 3mm dfn, ms8e, dd-pak, to-220 packages lt3023 dual 100ma, low noise, micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 40a, i sd <1a, dfn, ms10 packages lt 3024 dual 100ma/500ma, low noise, micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 60a, i sd <1a, dfn, tssop-16e packages lt3027 dual 100ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 40a, i sd <1a, dfn, ms10e packages lt3028 dual 100ma/500ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 60a, i sd <1a, dfn, tssop-16e packages lt3029 dual 500ma/500ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.215v, v do = 0.30v, i q = 55a, i sd <1a, dfn, msop-16e packages lt3032 dual 150ma positive/negative low noise, low dropout linear regulator v in : 2.3v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 30a, i sd <1a, 14-lead dfn package LT3080/ LT3080-1 1.1a, parallelable, low noise ldo 300mv dropout voltage (2-supply operation), low noise 40v rms , v in = 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set, directly parallelable (no op amp required), stable with ceramic capacitors, to-220, sot-223, msop and 3mm 3mm dfn sequencing supply application 10ms/div v out1 1v/div v out2 1v/div v shdn1 5v/div 3030 ta03b 237k 1% 113k 1% 3030 ta03a 237k 1% 54.9k 1% 1f in1 pwrgd1 pwrgd2 shdn1 in2 out1 byp1 adj1 adj2 byp2 out2 shdn2 1m 1m 1f 10nf 10nf 10f 22f v in1 3.3v v in2 2.5v v out1 1.8v 750ma v out2 1.5v 250ma gnd lt3030

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